1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to improved circuits for use in a semiconductor memory device for driving a word line control signal.
The present application claims priority based on Korean Patent Application Serial No. 15213/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Generally, known semiconductor memory devices use a high voltage, sometimes called a pumping voltage (hereinafter referred to as "VPP"), which is obtained by boosting the usual power supply voltage VCC, in order to improve speed of operation. In order to increase the current provided to memory cells or to compensate for a voltage drop as high as the threshold voltage (hereinafter referred to as a "VT") of an NMOS transistor of each memory cell, the pumping voltage VPP, preferably as high as VCC+VT, is provided in the semiconductor memory device.
"Bootstrap" circuits are known in the art for obtaining the pumping voltage VPP. In such circuits, the current consumed by the pumping voltage VPP is supplemented by the bootstrap method, thereby enabling a constant pumping voltage VPP. The greater the current consumed by the pumping voltage VPP, the greater the compensating current supplied by the bootstrap method. This requires an increase of the charge pump capacitance of the bootstrap circuit, causing an increase of the circuit size.
FIG. 1 is a circuit diagram showing a word line driver circuit according to the prior art, for driving word line control signals S1-S16. The word line drivers typically are part of a semiconductor RAM row decoder, which asserts one word line at a time in response to address input bits. Referring now to FIG. 1, first input signals /.phi.K1-/.phi.K16 exhibit the pumping voltage level VPP in the logic "high" state, and second input signals .phi.K1-.phi.K16 exhibit the supply voltage level VCC in the logic "high" state. Each of PMOS transistors T1 to T16 has is gate connected to a corresponding one of the first input signals and its source connected to the pumping voltage source VPP and its drain connected to a corresponding one of nodes N1 to N16.
Each of the NMOS transistors T17 to T32 has its gate connected to a corresponding one of second input signals .phi.K1-.phi.K15, its source connected to a ground voltage VSS and its drain connected to a corresponding one of the nodes N1 to N16. Each of the PMOS transistors T1 to T16 thus is connected in series with a corresponding one of the NMOS transistors T17 to T32 between the pumping voltage source VPP and the ground potential VSS. Each of the word line control signals S1 to S16 is output from a respective one of nodes N1 to N16 to the corresponding word line. Each drain of the PMOS transistors T1 to T16 and each drain of the NMOS transistors T17 to T32 are connected in common at the corresponding node N1 to N16, respectively. In operation, a word line control signal of logic "low" level is applied to a selected one of the word lines, whereas the remaining word line control signals of logic "high" levels are applied to the unselected word lines. For example, where the input signals select S16, the word line control signals S1 to S15 which are to be applied to the unselected word lines go from logic "low" levels to logic "high" levels, whereas the word line control signal S16 maintains a logic "low" level. In other words, the word line control signals S1 to S16 are active low.
FIG. 2 is a timing diagram of the word line control signals corresponding to the circuit of FIG. 1 in normal operation. In this illustration, the input signals together select the word line control signal S16. Referring to FIG. 2, the second input signals .phi.K1-.phi.K15 transition from the power supply voltage VCC levels to logic "low" levels, thus turning the NMOS transistors T17 to T31 OFF. Input signal .phi.K16 remains low. The first input signals, on the other hand, go from the pumping voltage VPP levels to logic "low" levels, thus turning the PMOS transistors T1 to T15 ON. Input signal /.phi.K16 remains at VPP. Consequently, the word line control signals S1 to S15 are pulled up from logic "low" levels to the pumping voltage VPP levels. Assuming that the capacitance required in charging a word line control signal S1 is C1, the voltage swing of the word line control signal S1 is ?VPP and the charge amount required from the pumping voltage source VPP to the word line control signal S1 is Q1, the charge amount Q1=C1 *?VPP. Where the number of the word line control signals S(i) is N, the total charge amount Qtot=Q1*N=(C1*)*N. The problem with this arrangement is the pumping voltage source VPP has to provide essentially the total charge amount Qtot to drive the word lines. This problem is exacerbated as DRAM devices, for example, grow to larger capacities, thereby requiring greater numbers of word lines and/or increases in word line length.